In the recent generations of technology, stress engineering and material innovations have replaced geometric scaling as the main contributors to the continued performance improvement in CMOS devices. For example, strained Si has been adopted as a promising option to improve complementary metal oxide semiconductor (CMOS)-based transistor device performance. More specifically, strained silicon on insulator (SSOI) technology is a promising way to increase charge carriers mobility in CMOS technologies such as, for example, FinFET, frigate, ultrathin body SOI and nanowires.
However, current methods to fabricate SSOI wafers are very expensive. For example, current manufacturing technologies require several masking layers in order to provide a stress material thereby increasing overall fabrication costs. Moreover, with smaller technology nodes, it becomes very difficult to obtain proper spacing between the S/D regions and the gate stack. Also, extremely close proximity in early embedded SiGe leads to highly variable devices since the location of device tailoring implants moves as a function of fill height. Also, integrating the stressors, with a controlled device and a replacement gate-flow high-k metal gate stack is expensive and complicated.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.